Anti-fuse memories are considered a non-volatile memory in which data is retained in the memory cell in the absence of power. An anti-fuse device is a structure alterable to a conductive state, or in other words, an electronic device that changes state from non-conducting to conducting. Equivalently, the binary states can be either one of high resistance and low resistance in response to electric stress, such as a programming voltage or current. Unlike other forms of non-volatile memory such as flash, ferro-electric and magnetic memories, the anti-fuse programming is intended to be irreversible. Hence anti-fuse memories are referred to as one time programmable (OTP) memories.
A DRAM-type memory array using a planar capacitors as an anti-fuse instead of as a storage capacitor is already known, as demonstrated in U.S. Pat. No. 6,667,902. FIG. 1 is a circuit diagram of such a memory cell, while FIGS. 2 and 3 show the planar and cross-sectional views respectively, of the known anti-fuse memory cell of FIG. 1. The memory cell of FIG. 1 includes a pass, or access transistor 10 for coupling a bitline BL to a bottom plate of anti-fuse device 12. A wordline WL is coupled to the gate of access transistor 10 to turn it on, and a cell plate voltage Vcp is coupled to the top plate of anti-fuse device 12 for programming anti-fuse device 12.
It can be seen from FIGS. 2 and 3 that the layout of access transistor 10 and anti-fuse device 12 is very straight-forward and simple. The gate 14 of access transistor 10 and the top plate 16 of anti-fuse device 12 are constructed with the same layer of polysilicon, which extend across active area 18. In the active area 18 underneath each polysilicon layer, is formed a thin gate oxide 20, also known as a gate dielectric, for electrically isolating the polysilicon from the active area underneath. On either side of gate 14 are diffusion regions 22 and 24, where diffusion region 24 is coupled to a bitline. Although not shown, those of skill in the art will understand that standard CMOS processing, such as sidewall spacer formation, lightly doped diffusions (LDD) and diffusion and gate silicidation, can be applied. While the classical single transistor and capacitor cell configuration is widely used, a transistor-only anti-fuse cell is further desirable due to the semiconductor array area savings that can be obtained for high-density applications. Such transistor-only anti-fuses must be reliable while simple to manufacture with a low cost CMOS process.
According to an embodiment of the present invention, FIG. 4A shows a cross-sectional view of an anti-fuse transistor that can be manufactured with any standard CMOS process. In the presently shown example, the anti-fuse transistor is almost identical to a simple thick gate oxide, or input/output MOS transistor with one floating diffusion terminal. The disclosed anti-fuse transistor, also termed a split-channel capacitor or a half-transistor, can be reliably programmed such that the fuse link between the polysilicon gate and the substrate can be predictably localized to a particular region of the device. The cross-section view of FIG. 4A is taken along line B-B′ of FIG. 4, being along the channel length of the device, which in the presently described embodiment is a p-channel device. Those of skill in the art will understand that the present invention can be implemented as an n-channel device.
Anti-fuse transistor 100 includes a variable thickness gate oxide 102 formed on the substrate channel region 104, a polysilicon gate 106, sidewall spacers 108, a field oxide region 109 a diffusion region 110, and an LDD region 114 in the diffusion region 110. A bitline contact 116 is shown to be in electrical contact with diffusion region 110. The variable thickness gate oxide 102 consists of a thick oxide and a thin gate oxide such that a portion of the channel length is covered by the thick gate oxide and the remaining portion of the channel length is covered by the thin gate oxide. Generally, the thin gate oxide is a region where oxide breakdown can occur. The thick gate oxide edge meeting diffusion region 110 on the other hand, defines an access edge where gate oxide breakdown is prevented and current between the gate 106 and diffusion region 110 is to flow for a programmed anti-fuse transistor. While the distance that the thick oxide portion extends into the channel region depends on the mask grade, the thick oxide portion is preferably formed to be at least as long as the minimum length of a high voltage transistor formed on the same chip.
In a preferred embodiment, the diffusion region 110 is connected to a bitline through a bitline contact 116, or other line for sensing a current from the polysilicon gate 106, and can be doped to accommodate programming voltages or currents. This diffusion region 110 is formed proximate to the thick oxide portion of the variable thickness gate oxide 102. To further protect the edge of anti-fuse transistor 100 from high voltage damage, or current leakage, a resistor protection oxide (RPO), also known as a salicide protect oxide, can be introduced during the fabrication process to further space metal particles from the edge of sidewall spacer 108. This RPO is preferably used during the salicidiation process for preventing only a portion of diffusion region 110 and a portion of polysilicon gate 106 from being salicided.
It is well known that salicided transistors are known to have higher leakage and therefore lower breakdown voltage. Thus having a non-salicided diffusion region 110 will reduce leakage. Diffusion region 110 can be doped for low voltage transistors or high voltage transistors or a combination of the two resulting in same or different diffusion profiles.
A simplified plan view of the anti-fuse transistor 100 is shown in FIG. 4B. Bitline contact 116 can be used as a visual reference point to orient the plan view with the corresponding cross-sectional view of FIG. 4A. The active area 118 is the region of the device where the channel region 104 and diffusion region 110 is formed, which is defined by an OD mask during the fabrication process. The dashed outline 120 defines the areas in which the thick gate oxide is to be formed via an OD2 mask during the fabrication process. More specifically, the area enclosed by the dashed outline 120 designates the regions where thick oxide is to be formed. OD simply refers to an oxide definition mask that is used during the CMOS process for defining the regions on the substrate where the oxide is to be formed, and OD2 refers to a second oxide definition mask different than the first.
Programming of anti-fuse transistor 100 is based on gate oxide breakdown to form a permanent link between the gate and the channel underneath. Gate oxide breakdown conditions (voltage or current and time) depend primarily on i) gate dielectric thickness and composition, ii) defect density, and iii) gate area, gate/diffusion perimeter. The combined thick and thin gate oxide of anti-fuse transistor 100 results in a locally lowered gate breakdown voltage, in particular an oxide breakdown zone, in the thin gate oxide portion of the device. Anti-fuse transistor 100 is but one type of anti-fuse device which can be used in an OTP memory. Those skilled in the art will understand that different types of anti-fuse devices are programmed in a similar manner.
As with any fabricated semiconductor memory device, random defects can occur during manufacturing. More specifically, memory cells can suffer from physical defects that alter its characteristics. Such defects can render the OTP memory inoperable, since data may not be reliably stored in the defective cells. In a newly manufactured anti-fuse memory array, all the cells should be read as having an unprogrammed logic state. For example, an unprogrammed state logic state can correspond to a “0”. However, due to manufacturing defects, some of the anti-fuse cells will leak current. In the present example, anti-fuse cells which leak current will read as a logic “1” state, which corresponds to a programmed state of the cell. These types of defective cells are referred to as leaky cells. Conversely, some anti-fuse cells may be difficult to program, thereby reading out a logic “0” state when it should be reading out as a logic “1” state. These types of defective cells are referred to as weak cells.
In order to improve overall manufacturing yield, redundancy schemes have been developed to repair memory arrays having defective cells. A well known redundancy technique of replacing rows and/or columns containing a defective cell with spare rows and/or columns can be used. However, such techniques introduce significant logic overhead for re-routing addresses while trying to ensure transparent operation and minimum diminished performance to the end user.
Examples of prior redundancy schemes are disclosed in the following US patents. In U.S. Pat. No. 6,421,799, a redundant ROM stores parity bits for rows and columns of main memory. A testing circuit calculates a parity for each row and column. In U.S. Pat. No. 6,944,083 a good copy of the sensitive data is stored in a different physical location. If tampering of memory is detected by comparing data stored in main memory with data stored in redundancy, data in the main memory is identified as unusable and data retrieved from redundant memory is used instead. In U.S. Pat. No. 7,047,381 multistage programming is implemented in the OTP array with use of the redundant rows. In U.S. Pat. No. 7,003,713 an OTP module receives encoded host data from the host integrated circuit and provides a copy of corrected host data to the host integrated circuit.
Most redundancy schemes require significant additional logic, which ultimately increases the chip area or macro footprint. Therefore a new redundancy scheme that minimizes logic overhead while maximizing overall yield is needed.